Process for forming low defect density heterojunctions

ABSTRACT

A method for forming a low defect density heterojunction between a first and a second compound, the first and second compounds each includes a group III element combined with a group V element in the periodic table, the method includes the steps of introducing in the deposition chamber the flux of the group III element for the first compound at substantially the same time while introducing in the deposition chamber a flux of the group V element for the second compound, stopping the flux of the group III element for the first compound after a first predetermined time period, stopping the flux of the group V element for the first compound after a second predetermined time period, and introducing in the deposition chamber a flux of the group III element the group V element for the second compound.

CLAIM OF PRIORITY UNDER 35 U.S.C. § 120

This application is a continuation of and claims the benefit andpriority of U.S. application Ser. No. 11/521,330, now U.S. Pat. No.______, entitled “PROCESS FOR FORMING LOW DEFECT DENSITYHETEROJUNCTIONS,” filed on Sep. 14, 2006, which is assigned to theassignee hereof and hereby expressly incorporated by reference herein.

STATEMENT REGARDING GOVERNMENT RIGHTS

This invention was made with Government support under contractN66001-01-C-8032 awarded by the Department of Defense, DARPA, US Navy,Space & Naval Warfare Systems (SPAWAR). The Government has certainrights in the invention.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to a semiconductor fabrication method.More particularly, the invention relates to a process for forming lowdefect density heterojunctions in semiconductor devices.

2. Description of Related Art

In advanced semiconductor devices, junctions between two differentsemiconductor materials are typically used to improve the performance ofthe device. These junctions, composed of layers of dissimilarsemiconductor material, are known in the art as heterojunctions. Thesemiconductor materials used at the heterojunctions generally havenon-equal band gaps and electron affinities.

A heterojunction has two pieces of semiconductor materials directly incontact with one another. It is often desirable to induce a specifictype of bonding at the heterojunction. For example, forcing theheterojunction to have indium antimonide (InSb)-like bonding at analuminum antimonide (AlSb) to indium arsenide (InAs) heterojunction forimproved electron mobility, as described in G. Tuttle, H. Kroemer and J.English, “Effects of Interface layer sequencing on transport propertiesof InAs/AlSb quantum wells”, J.A.P.- Vol. 67, No. 6, 15 Mar. 1990, pp.3033. Another example is forcing the heterojunction to have InSb-likebonding in a gallium antimonide (GaSb) to indium arsenide (InAs)superlattice grown on a GaSb substrate for lattice strain compensation.

A common method for achieving this desired bonding is using MolecularBeam Epitaxy (MBE) for growth. One advantage of using MBE growth is lowtemperature processing, which minimizes out-diffusion and autodoping inthe semiconductor material. Another advantage is the precise control ofdoping profiles and deposition thickness that MBE allows. The MBEprocess can be used to control the bonding of group III-V materials. Forexample, the MBE process can be used to produce a GaSb to InAsheterojunction with InSb bonding, as opposed to GaAs bonding, at theheterojunction.

The prior art process of forming a AlGaSb to InAs heterojunctionincludes the following steps. First, AlGaSb is deposited on a basesubstrate. During the growth of AlGaSb, the aluminum (Al) and gallium(Ga) fluxes are stopped, and the surface is soaked with the antimony(Sb) flux. This covers any exposed aluminum or gallium atoms with anantimony atom, and any excess antimony should re-evaporate under typicalMBE growth temperatures and fluxes. Next, the antimony flux is stopped,and a monolayer of indium is deposited. This indium monolayer is bondedto the antimony atoms on the surface of the substrate. After thedeposition of the monolayer of indium, the indium flux is continued anda suitable arsenic flux is initiated, resulting in the growth of InAs.This method of forming the heterojunction is called “forcing InSb-likebonding”.

This procedure of interrupting growth, depositing a monolayer of thedesired group III material, and then continuing growth has beendiscussed in the prior art. Unfortunately, this procedure causes defectsat certain heterojunctions. For example, forcing InSb-like bonding at anInAs to AlGaSb heterojunction has resulted in tiny oval defects 113nucleated at the heterojunction, as shown in FIG. 1. Meanwhile, forcingInSb-like bonding at an AlSb to InAs heterojunction does not result innucleated defects. The tiny oval defects 113, shown in FIG. 1, formed atthe InAs to AlSb heterojunction, have been correlated with excessleakage currents between metal gates (e.g. Schottky gates) and channels.If the metal gate crosses one of these defects, excess leakage from thegate to the channel of the transistor occurs. Hence, with an increasingdemand for improved semiconductor fabrication methods, there remains acontinuing need for a process for forming semiconductor materials with alow defect density.

BRIEF DESCRIPTION OF THE DRAWINGS

The exact nature of this invention, as well as the objects andadvantages thereof, will become apparent from consideration of thefollowing specification in conjunction with the accompanying drawings inwhich like reference numerals designate like parts throughout thefigures.

FIG. 1 is a differential interference contrast optical micrograph of thesurface of a HFET layer structure, illustrating the effect of an InAs toAlSb heterojunction forced to have InSb-like bonding, resulting in ahigh defect density, grown according to a prior art semiconductor growthmethod.

FIG. 2 is an exemplary diagram depicting the time sequence of events forcontrolling elemental flux in a deposition chamber, according to a priorart semiconductor fabrication method.

FIG. 3 is an exemplary flow chart depicting a method for forming lowdefect density heterojunctions, according to an embodiment of theinvention.

FIG. 4 is a cross-sectional view of an MBE system.

FIG. 5 schematically shows in cross-section a semiconductor compoundAlGaSb deposited on the surface of a substrate according to anembodiment of the invention.

FIG. 6 schematically shows in cross-section a layer of group V element,antimony, being deposited on the surface of the AlGaSb according to anembodiment of the invention.

FIG. 7 schematically shows a monolayer of the group III element, indium,being deposited, according to an embodiment of the invention.

FIG. 8 schematically shows in cross-section a layer of indium arsenide(InAs) being deposited according to an embodiment of the invention.

FIG. 9 schematically shows in cross-section a layer of arsenic depositedat the heterojunction, according to an embodiment of the invention.

FIG. 10 schematically shows in cross-section the deposition of AlGaSb,according to an embodiment of the invention.

FIG. 11 is an exemplary diagram depicting the time sequence of eventsfor controlling elemental flux in the deposition chamber to produce lowdefect density heterojunctions, according to an embodiment of theinvention.

FIG. 12 is a differential interference contrast optical micrograph ofthe surface of an HFET layer structure illustrating a layer structurewith low defect density, according to the method embodying theinvention.

SUMMARY OF THE INVENTION

A method for forming a low defect density heterojunction between a firstsemiconductor compound (i.e. InAs) and a second semiconductor compound(i.e. AlGaSb). The method controls the sequential deposition of thematerials to control the detailed bonding at the heterojunctions, andminimize the nucleation of morphological defects. The method comprisesdepositing the first semiconductor compound on a substrate byintroducing in a deposition chamber a flux of the group III element andthe group V element for the first semiconductor compound, covering thedeposited first semiconductor compound with a layer of the group Velement for the first semiconductor compound to prevent the group IIIelement for the first semiconductor compound from being exposed, anddepositing the second semiconductor compound on the layer of the group Velement for the first semiconductor compound by introducing in thedeposition chamber a flux of the group III element and the group Velement for the second semiconductor compound. This may produce anunforced heterojunction between the first and second semiconductorcompounds.

In one embodiment, the group III and V elements of the firstsemiconductor compound is indium (In) and arsenic (As), respectively,while the group III and V elements of the second semiconductor compoundis aluminum (Al), gallium (Ga) and antimony (Sb), respectively. Inanother embodiment, the group III and V elements of the firstsemiconductor compound is gallium (Ga) and antimony (Sb), respectively,while the group III and V elements of the second semiconductor compoundis in https://exweb.panasonic.co.jp/ipro/ceeh01/dium (In) and arsenic(As), respectively.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Methods and systems that implement the embodiments of the variousfeatures of the invention will now be described with reference to thedrawings. The drawings and the associated descriptions are provided toillustrate embodiments of the invention and not to limit the scope ofthe invention. Reference in the specification to “one embodiment” or “anembodiment” is intended to indicate that a particular feature,structure, or characteristic described in connection with the embodimentis included in at least an embodiment of the invention. The appearancesof the phrase “in one embodiment” or “an embodiment” in various placesin the specification are not necessarily all referring to the sameembodiment. Throughout the drawings, reference numbers are re-used toindicate correspondence between referenced elements. In addition, thefirst digit of each reference number indicates the figure in which theelement first appears.

FIG. 1 is a differential interference contrast optical micrograph of thesurface of an HFET layer structure, illustrating a layer with a highdefect density, according to a prior art semiconductor fabricationmethod. The optical micrograph 111 shows nucleated defects 113 on thesurface. The defects 113 are randomly distributed across the surface.These defects 113 contribute to excess leakage currents from atransistor's gate (not shown). Although the prior method of forcingInSb-like bonding at the InAs to AlGaSb heterojunction results innucleated defects 113, the new method of forcing InSb-like bonding atthe InAs to AlGaSb heterojunction does not result in defects.

FIG. 2 is an exemplary diagram depicting the time sequence of events forcontrolling elemental fluxes to produce InSb-like bonding at aheterojunction, according to the prior art semiconductor fabricationmethod. Since the procedure of interrupting growth of AlGaSb, depositingan indium monolayer, and then continuing growth of InAs produces nodefects 113, this procedure suffices in the formation of an AlGaSb toInAs heterojunction. However, heterojunctions that do experiencenucleated defects 113 require a different growth procedure, as describedherein.

FIG. 3 is an exemplary flow chart depicting a method for forming lowdefect density heterojunctions according to an embodiment of theinvention. The steps for carrying out this method are schematicallyillustrated in FIGS. 4-11. Since the forced InAs to AlSb heterojunctionwas identified to be the source of the defects, the method embodying theinvention will be discussed in the context of fabricating a low defectInAs to AlSb heterojunction. Nevertheless, this method can also be usedfor other heterojunctions between different semiconductor compounds,such as InAs to GaSb heterojunctions, including those that do notexperience substantial defect density so as to alleviate the need fordetermining which forced heterojunctions do or do not have defects.

In Step 305, a substrate 411 is prepared for growth by placing it in anMBE deposition chamber 413. The base substrate 411 can be a silicon orgallium arsenide (GaAs) wafer. A cross-sectional view of the apparatuswith the base substrate 411 is illustrated in FIG. 4.

Next, in step 310, a constant flux of group III and V elements areintroduced into the chamber at inlets 415, 416 and 417, respectively. Inthis example, the group III elements are aluminum (Al) and gallium (Ga),and the group V element is antimony (Sb). These elements react with oneanother to form an aluminum gallium antimonide (AlGaSb) layer 510. FIG.5 shows AlGaSb layer 510 deposited on the surface of the substrate 411,collectively referred to as multilayer 500.

After a predetermined period, which is a function of the desiredthickness of the AlGaSb, the fluxes of the group III elements, aluminum(Al) and gallium (Ga), are stopped in Step 315. Since there are nolonger aluminum (Al) or gallium (Ga) fluxes in the deposition chamber413, only the group V flux of antimony (Sb) is impinging on the surfaceof the AlGaSb, step 320. This covers any exposed aluminum (Al) orgallium (Ga) with antimony (Sb) layer 610, as shown in FIG. 6. Anyexcess antimony (Sb) should re-evaporate under typical MBE growthtemperatures and fluxes. Once the antimony (Sb) layer is formed, theflux of the group V element, antimony (Sb), is stopped, step 325. Thesubstrate 411, compound A (AlGaSb) and the antimony layer 610 arecollectively referred to as multilayer 600.

In one method embodying the invention, a monolayer of the group IIIelement, indium (In), is deposited on AlGaSb at the heterojunction instep 330. To create an InSb-like bonding at the AlGaSb to InAsheterojunction, a flux of the group III element, indium (In), isintroduced in the deposition chamber 413https://exweb.panasonic.co.jp/ipro/ceeh01/. The indium reacts withantimony 610 to form an InSb layer 710 on the surface of the multilayer600, as shown in FIG. 7.

After the deposition of a monolayer of indium (In), a group V element,arsenic (As) flux, is initiated to grow an InAs layer 810 at step 335.FIG. 8 is an exemplary diagram showing an InAs layer 810 growing on thesurface of the InSb layer 710. The deposited layers are collectivelyreferred to as multilayer 800.

At step 340, the growth of the InAs layer 810 is terminated and thesurface is soaked with group V element, arsenic (As), as shown in FIG.9. This covers any exposed indium (In) with arsenic (As).

Next, in step 345, the arsenic flux is stopped and fluxes of group IIIelements, aluminum (Al) and gallium (Ga), and group V element, antimony(Sb) are introduced into the deposition chamber 413. The elements, Al,Ga and Sb, react with one another to form an AlGaSb layer 1010, as shownin FIG. 10. Once the desired thickness of the AlGaSb layer 1010 isachieved, the group III (Al and Ga) and group V (Sb) fluxes are stopped,and growth is terminated in step 350.

FIG. 11 is an exemplary diagram depicting the time sequence of eventsfor controlling elemental flux in the deposition chamber 413 to producelow defect density heterojunctions, according to one embodiment of theinvention. The diagram shows that aluminum, gallium and antimony fluxesare introduced in the deposition chamber 413, and then the aluminum andgallium fluxes are stopped, while the flux of antimony continues for apredetermined time period. Then a monolayer of indium is deposited, andan InAs layer is grown.

To form a low defect density InAs to AlGaSb heterojunction, the indiumflux is stopped, and the arsenic flux continues, to fully bond thesurface of the InAs layer 810. Next, the arsenic flux is stopped, andaluminum, gallium and antimony fluxes are introduced in the chamber 413to react and deposit AlGaSb. Finally, the aluminum, gallium and antimonyfluxes are stopped.

FIG. 12 is a differential interference contrast optical micrograph ofthe surface of an HFET layer structure illustrating a layer structurewith low defect density, according to the method embodying theinvention. The optical micrograph 1211 shows no nucleated defects 113.Thus, the InAs to AlGaSb heterojunction, fabricated according to themethod embodying the invention, reduces the nucleated defects 113 thatformed from prior art techniques. With a low defect 113 density, theInAs to AlSb heterojunction minimizes leakage currents from gates.

While certain exemplary embodiments have been described and shown in theaccompanying drawings, it is to be understood that such embodiments aremerely illustrative of and not restrictive on the broad invention, andthat this invention not be limited to the specific constructions andarrangements shown and described, since various other changes,combinations, omissions, modifications and substitutions, in addition tothose set forth in the above paragraphs, are possible. For example,other compounds can be used at the unforced heterojunction from thosedescribed above to achieve a low defect density at the interface. Thoseskilled in the art will appreciate that various adaptations andmodifications of the just described preferred embodiment can beconfigured without departing from the scope and spirit of the invention.Therefore, it is to be understood that, within the scope of the appendedclaims, the invention may be practiced other than as specificallydescribed herein.

1. A method for forming a low defect density heterojunction between afirst compound and a second compound, the first and second compoundseach including a group III element and a group V element in the periodictable, the method comprising: simultaneously depositing a first groupIII element and a first group V element to form a first compound layerincluding the first compound during a first period of time; continuouslydepositing the first group V element while stopping the depositing ofthe first group III element to form a first junction surfacesubstantially covering the first compound layer during a second periodof time, the first junction surface including the first group V elementand substantially free of the first group III element; andsimultaneously depositing a second group III element and a second groupV element to form a second junction surface and a second compound layerincluding the second compound during a third period of time, the secondjunction surface substantially covering the first junction surface, thesecond compound layer formed on the second junction surface, such thatthe first and second junction surfaces combine to form the low defectdensity heterojunction.
 2. The method of claim 1, wherein the firstgroup III element is indium (In).
 3. The method of claim 1, wherein thesecond group V element is antimony (Sb).
 4. The method of claim 1,wherein the first group V element is arsenic (As).
 5. The method ofclaim 1, wherein the second group III element is selected from a groupconsisting of aluminum (Al), gallium (Ga), and combinations thereof. 6.The method of claim 1, wherein the first group V element is chemicallybonded to the first group III element to form the first compound, andwherein the second group V element is chemically bonded to the secondgroup III element to form the second compound.
 7. The method of claim 1,wherein the second period of time comes after the first period of time,and the third period of time comes after the second period of time. 8.The method of claim 1, wherein the second junction surface consistsessentially of the second group III element.
 9. The method of claim 1,wherein the first group III element is different from the second groupIII element, and wherein the first group V element is different from thesecond group V element.
 10. A method for forming a low defect densityheterojunction between a first compound and a second compound, the firstand second compounds each including a group III element and a group Velement in the periodic table, the method comprising: simultaneouslyintroducing a first flux of a first group III element and a second fluxof a first group V element to form a first compound layer including thefirst compound; stopping the first flux of the first group III elementwhile continuing the second flux of the first group V element to form afirst junction surface substantially covering the first group IIIelement of the first compound layer; and stopping the second flux of thefirst group V element while introducing a third flux of a second groupIII element and a fourth flux of a second group V element to form asecond junction surface and a second compound layer including the secondcompound.
 11. The method of claim 10, wherein the second junctionsurface substantially covers the first junction surface, and the secondcompound layer is formed on the second junction surface, such that thefirst and second junction surfaces combine to form the low defectdensity heterojunction.
 12. The method of claim 10, wherein the firstgroup III element is indium (In) and the first group V element isarsenic (As).
 13. The method of claim 10, wherein second group V elementis antimony (Sb), and the second group III element consists of anelement selected from a group consisting of aluminum (Al), gallium (Ga),and combinations thereof.
 14. The method of claim 10, wherein the secondjunction surface consists essentially of the second group III element.15. The method of claim 10, wherein the first group III element isdifferent from the second group III element, and wherein the first groupV element is different from the second group V element.
 16. The methodof claim 10, further comprising: stopping the third flux of the secondgroup III element and the fourth flux of the second group V element. 17.A hetrostructure field effect transistor (HFET) device comprising: afirst compound layer having a first chemical compound; a group V elementjunction surface covering the first compound layer; and a secondcompound layer having a second chemical compound, and forming on thegroup V element junction surface.
 18. The device of claim 17, whereinthe first chemical compound includes a first group III element and afirst group V element, wherein the second chemical compound includes asecond group III element and a second group V element.
 19. The device ofclaim 17, further comprising a group III element junction surfacecovering the group V element junction surface, the group III elementjunction surface combining with the group V element junction surface toform a low defect density heterojunction between the first compoundlayer and the second compound layer.
 20. The device of claim 18,wherein: the first group III element is indium (In), the first group Velement is arsenic (As), the second group III element is selected from agroup consisting of aluminum (Al), gallium (Ga), and combinationsthereof, and the second group V element is antimony (Sb).